EE - Design and Application of Volatile Charge Coupled Memory
In this project, we are studying the charge coupled device in the 3D NAND architecture for volatile memory application. As the large language models rapidly evolve, high density and performance buffer memory is more important then ever. The existing solution based on stacked DRAM architecture is cost prohibitive. In this regard, adopting the 3D NAND compatible architecture while offering DRAM like performance is highly attractive. In this project, we are going to study the charge coupled device from device simulation and project the memory density and performance. Then we will explore applications that can exploit the unique memory architecture.
The Nanoelectronic Devices and Systems lab directed by Prof. Kai Ni is working on the foundational technology that can enable the next generation computing and storage. Our group works on the state-of-the-art semiconductor devices that can potentially transform the modern memory hierarchy and support energy efficient computing. By working on the project, the student has a chance to developing necessary skills to work in semiconductor industry. In addition, the lab is well connected with industry, such as Samsung, Intel, Micron, etc. The students will have a chance to interact with industry for career development.